Semiconductor devices frequently have the ability to generate voltage or current references on chip. Such references are used during the operation of the chip, and sometimes other reference or current voltages are scaled from them.
While the voltage or current references generated by chips of the same nominal type are theoretically identical, in practice, because of process variations in the manufacturing of the chips, such voltage or current references provided by individual chips may be somewhat different. To correct the voltage or current references so that all chips generate the identical preselected voltage or current reference within some acceptable error, a trimming capability may be incorporated in the chips. A trim code may be stored in each chip which corresponds to the amount which the voltage or current reference generated by that chip needs to be adjusted in order to provide the preselected voltage or current reference. A particular semiconductor device which may have trimmable voltage or current reference generating capability is a dynamic random access memory (DRAM). While the present invention may be utilized in connection with providing trimmed voltage or current references for DRAMs, it is not so limited and may be used in connection with other semiconductor devices having trimmable voltage or current reference generating capability.
It is during the testing of the chips that the trim codes are established for the devices. In the prior art, a tester apparatus was provided, and each device under test (DUT) was individually fed by the tester with a sequence of trim codes for a particular reference. The trimmed voltage or current reference was fed back to the tester and compared with a preselected voltage or current reference value. By testing multiple iterations determined by the trim code sequencing, the preferred trim code was determined by the tester, and then it was necessary for the tester to reprogram the DUT with the preferred trim code in order to continue subsequent testing of the DUT. The testing of chips with the prior art methodology was time consuming because each DUT needed to be trimmed individually, and each DUT needed to be reprogrammed with the preferred trim code prior to further testing.